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| 车彬, 樊晓桠 |
（西北工业大学 航空微电子中心，陕西 西安 710072） |
 摘要：超深亚微米工艺和基于可复用嵌入式IP模块的系统级芯片（SoC）设计方法使测试面临新的挑战，需要研究开发新的测试方法和策略。介绍了可测性设计技术常用的几种方法，从芯核级综述了数字逻辑模块、模拟电路、内存、处理器、第三方IP核等的测试问题，并对SoC可测性设计策略进行了探讨，最后展望了SoC测试未来的发展方向。 |
| 关键词：片上系统；可测性设计；扫描测试 |
| 中图分类号：TP303文献标识码：A文章编号：1000-8829(2009)06-0001-04 |
| esearch of Design-on-Testability for SoC |
| CHE Bin, FAN Xiao-ya |
| (Aviation Microelectronic Center,Northwestern Polytechnical University,Xi’an 710072,China) |
| Abstract：A comprehensive survey of the up-to-date design for testability(DFT) methods and testing technologies for system-on-a-chip(SoC) is presented.The very deep sub micrometer technics and the system-on-a-chip(SoC) based on reusable embedded IP(intellectual property) pose new challenges for test,and the new test methodology and strategy for SoC are needed. Some common techniques for VLSI DFT are summarized.The techniques of DFT and testing for embedded cores of digital,analog/mixed-signal,memory,processor and third-party IP core are introduced respectively.The DFT strategy of SoC design is discussed.Finally,some future directions in DFT and test technologies for SoC are indicated. |
| Key words：system-on-a-chip(SoC);design for testability;scan test |
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